Products > Integrated Circuits (ICs) > Clock & Timer ICs > 82P33831ABAG
82P33831ABAG 144-LBGA
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  • 82P33831ABAG
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82P33831ABAG

REPLACES 82P33831BAG SYNCE 1588 PLL

Manufacturer :
Integrated Device Technology, Inc. (Renesas)
Package/Case :
144-LBGA
Product Categories :
Clock_Timing - Application Specific
Datasheet:
82P33831ABAG PDF
RoHs Status:
Lead free / RoHS Compliant
In-stock:
612

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82P33831ABAG Product Details

The 82P33831ABAG Synchronization Management Unit (SMU) provides tools to manage timing references, clock sources and timing paths for IEEE 1588 and Synchronous Ethernet (SyncE) based clocks. The device supports up to three independent timing paths that control: IEEE 1588 clock synthesis; SyncE clock generation; and general purpose frequency translation. The device supports physical layer timing with Digital PLLs (DPLLs) and it supports packet based timing with Digitally Controlled Oscillators (DCOs). Input-to-input, input-to-output and output-to-output phase skew can all be precisely managed. The device outputs low-jitter clocks that can directly synchronize 40GBASE-R, 10GBASE-R and 10GBASE-W and lower-rate Ethernet interfaces; as well as CPRI/OBSAI, SONET/SDH and PDH interfaces and IEEE 1588 Time Stamp Units (TSUs).

Feature

  • SMU allows any IEEE 1588 software, running on an external processor, to control the generation of electical clocks, and to access and control physical layer synchronization
  • Supports Telecom Boundary Clock (T-BC) and Telecom Time Slave Clock (T-TSC) applications per G.8273.2 with physical layer frequency support to the DCOs
  • Physical layer clocks comply with ITU-T G.8262 for Synchronous Ethernet Equipment Clock (EEC), and G.813 for Synchronous Equipment Clock (SEC), and Telcordia GR-253-CORE for Stratum 3 and SONET Minimum Clock (SMC)
  • System-wide precise 1PPS (Pulse Per Second) edge alignment is supported with programmable input-to-input, input-to-output and output-to-output phase delays: sub-ns resolution
  • 24 hour time holdover is supported by DCOs with fine frequency resolution (1.7e-16)
  • Generates clocks for: 10GBASE-R, 10GBASE-W, 40GBASE-R and CPRI/OBSAI interfaces without external jitter attenuators: jitter generation <0.3 ps RMS (10 kHz to 20 MHz)
  • Generates clocks for: Ethernet, SONET/SDH and PDH interfaces: jitter generation <1 ps RMS (12 kHz to 20 MHz)
  • IEEE 1588 grand master applications are supported by locking to 1 PPS (Pulse Per Second) references from GPS or other GNSS sources
  • Eases local oscillator sourcing by supporting any of eight common TCXO/OCXO frequencies for the System Clock: 10 MHz, 12.8 MHz, 13 MHz, 19.44 MHz, 20 MHz, 24.576 MHz, 25 MHz or 30.72 MHz
  • Automatically loads configuration from an external EPROM after reset without processor intervention
  • 144 pin CABGA package
  • Supported by

82P33831ABAG Block Diagram
(Picture: Diagram)

Technical Parameters

PLL Yes Frequency Max 650MHz
Main Purpose Ethernet, SONET/SDH, Stratum Voltage Supply 1.8V, 3.3V
Input CMOS, LVDS, PECL Operating Temperature -40??C ~ 85??C
Output CMOS, LVDS, PECL Mounting Type Surface Mount
Number of Circuits 3 Package / Case 144-LBGA
Ratio Input:Output 14:14 Supplier Device Package 144-CABGA (13x13)
Differential Input:Output Yes/Yes

82P33831ABAG Documents

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