Bus Transceivers 16-Bit Bus Trcvr/Reg W/3-St Otpt
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74AC16652DLG4 Product Details
The 'AC16652 are 16-bit bus transceivers that consist of D-type flip-flops and control circuitry arranged for multiplexed transmission of data directly from the data bus or from the internal storage registers. They can be used as two 8-bit transceivers or one 16-bit transceiver.
Complementary output-enable (OEAB and ) inputs are provided to control the transceiver functions. Select-control (SAB and SBA) inputs are provided to select whether real-time or stored data is transferred. A low input level selects real-time data, and a high input level selects stored data. The circuitry used for select control eliminates the typical decoding glitch that occurs in a multiplexer during the transition between stored and real-time data. Figure 1 illustrates the four fundamental bus-management functions that can be performed with the 'AC16652.
Data on the A or B bus, or both, can be stored in the internal D flip-flops by low-to-high transitions at the appropriate clock (CLKAB or CLKBA) inputs regardless of the levels on the select-control or output-enable inputs. When SAB and SBA are in the real-time transfer mode, it is also possible to store data without using the internal D-type flip-flops by simultaneously enabling OEAB and . In this configuration, each output reinforces its input. Thus, when all other data sources to the two sets of bus lines are at high impedance, each set of bus lines remains at its last state.
The 74AC16652DLG4 is packaged in TI's shrink small-outline package (DL), which provides twice the I/O pin count and functionality of standard small-outline packages in the same printed-circuit-board area.
The 54AC16652 is characterized for operation over the full military temperature range of -55°C to 125°C. The 74AC16652DLG4 is characterized for operation from -40°C to 85°C.
The data-output functions may be enabled or disabled by a variety of level combinations at OEAB or . Data-input functions are always enabled; i.e., data at the bus terminals is stored on every low-to-high transition on the clock inputs.
Select control = L; clocks can occur simultaneously.Select control = H; clocks must be staggered in order to load both registers.Figure 1. Bus-Management Functions
- Members of the Texas Instruments Widebus TM Family
- Independent Registers and Enables for A and B Buses
- Multiplexed Real-Time and Stored Data
- Flow-Through Architecture Optimizes PCB Layout
- Distributed VCC and GND Pin Configurations MinimizeHigh-Speed Switching Noise
- EPIC TM (Enhanced-Performance Implanted CMOS)1-m Process
- 500-mA Typical Latch-Up Immunity at 125°C
- Package Options Include Plastic 300-mil Shrink Small-Outline(DL) Packages Using 25-mil Center-to-Center Pin Spacings and380-mil Fine-Pitch Ceramic Flat (WD) Packages Using 25-milCenter-to-Center Pin Spacings
|Logic Type||Registered Transceiver||Maximum Operating Temperature||+ 85 C|
|Logic Family||AC||Package / Case||SSOP-56|
|Number of Channels per Chip||16||Packaging||Tube|
|Input Level||CMOS||Function||Bus Transceiver / Register|
|Output Level||CMOS||Maximum Power Dissipation||1.4 W|
|Output Type||3-State||Minimum Operating Temperature||- 40 C|
|High Level Output Current||- 24 mA||Mounting Style||SMD/SMT|
|Low Level Output Current||24 mA||Number of Circuits||2|
|Propagation Delay Time||17.3 ns||Polarity||Non-Inverting|
|Supply Voltage Max||5.5 V||Factory Pack Quantity||20|
|Supply Voltage Min||3 V|
74AC16652 Family Datasheet
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