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53621
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53621

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Model 53621 3-Ch 200 MHz A/D with DDC & 2-Ch 800 MHz D/A with DUC, Virtex-6 FPGA-3U VPX

Manufacturer :
Pentek
Product Categories :
Programmable Logic ICs
Datasheet:
53621 PDF
RoHs Status:
Lead free / RoHS Compliant
In-stock:
1020

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53621 Product Details

Model 53621 is a member of the CobaltTM family of high performance 3U VPX boards based on the Xilinx Virtex-6 FPGA. A multichannel, high-speed data converter with a programmable DDC, it is suitable for connection to HF or IF ports of a communications or radar system. Its built-in data capture and playback features offer an ideal turnkey solution. The 53621 includes three A/Ds, one upconverter, two D/As and four banks of memory. It features built-in support for PCI Express over the 3U VPX backplane.

Model is a member of the CobaltTM family of high performance 3U VPX boards based on the Xilinx Virtex-6 FPGA. A multichannel, high-speed data converter with a programmable DDC, it is suitable for connection or IF ports of a communications or radar system. Its built-in data capture and playback features offer an ideal turnkey solution. The 53621 includes three A/Ds, one upconverter, two D/As and four banks of memory. It features built-in support for PCI Express over the 3U VPX backplane. sition modules. IP modules for either DDR3 or QDRII+ memories, a controller for all data clocking and synchronization functions, a test signal generator, an Aurora gigabit serial interface, and a PCIe interface complete the factory-installed functions and enable the 53621 to operate as a complete turnkey solution, without the need to develop any FPGA IP.

For applications that require specialized function, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits include all of the factoryinstalled modules as documented source code. Developers can integrate their own IP with the Pentek factory-installed functions or use the GateFlow kit to completely replace the Pentek IP with their own.

Model 53621 COTS (left) and rugged version The Pentek Cobalt Architecture features a Virtex-6 FPGA. All of the board's data and control paths are accessible by the FPGA, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt Architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with factory-installed applications ideally matched to the board's analog interfaces. The 53621 factory-installed functions include three A/D acquisition and a D/A waveform playback IP modules. Each of the three acquisition IP modules contains a powerful, programmable DDC IP core. The waveform playback IP module contains an intrepolation IP core, ideal for matching playback rates to the data and decimation rates of the acquiRF In

The Virtex-6 FPGA can be populated with a variety of different FPGAs to match the specific requirements of the processing task. Supported FPGAs include: or SX475T. The SXT parts feature 2016 DSP48E slices and are ideal for modulation/demodulation, encoding/decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources, one of the lower-cost LXT FPGAs can be installed. Option -104 provides 20 pairs of LVDS connections between the FPGA and the VPX P2 connector for custom I/O.

Features

Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs Three 200 MHz 16-bit A/Ds Three multiband DDCs (digital downconverters) One DUC (digital upconverter) Two 800 MHz 16-bit D/As Multiboard programmable beamformer of DDR3 SDRAM MB of QDRII+ SRAM Sample clock synchronization to an external system reference LVPECL clock/sync bus for multiboard synchronization 3U VPX form factor provides a compact, rugged platform Compatible with several VITA standards including: VITA-46, VITA-48 and VITA-65 (OpenVPXTM System Specification) Ruggedized and conductioncooled versions available

TTL Gate / Trig TTL Sync / PPS Sample Clk Reset Gate A/D Gate D/A Sync / PPS A/D Sync / PPS D/A
QDRII+ option 160 DDR3 option 165 DDR3 SDRAM MB DDR3 SDRAM 512 MB CROSSBAR SWITCH
Pentek, Inc. One Park Way Upper Saddle River New Jersey 07458

setting that ranges from to s, where s is the A/D sampling frequency. Each DDC can have its own unique decimation setting, supporting as many as three different output bandwidths for the board. Decimations can be program-med from to 65,536 providing a wide range to satisfy most applications. The decimating filter for each DDC accepts a unique set of user-supplied 18-bit coefficients. The 80% default filters deliver an output bandwidth of 0.8*s/N, where N is the decimation setting. The rejection of adjacent-band components within the 80% output bandwidth is better than 100 dB. Each DDC delivers a complex output stream consisting 16-bit Q samples at a rate of s/N. power level of any DDC core falls below or exceeds a programmable threshold. A programmable summation block provides summing of any of the three DDC core outputs. An additional programmable gain stage compensates for summation change bit growth. A power meter and threshold detect block is provided for the summed output. The output is then directed back into the A/D Acquisition IP Module 1 FIFO for reading over the PCIe. For larger systems, multiple 53621's can be chained together via a built-in Xilinx Aurora gigabit serial interface through the VPX P1 connector. This allows summation across channels on multiple boards.

The 53621 features three A/D Acquisition IP Modules for easily capturing and moving data. Each module can receive data from any of the three A/Ds, a test signal generator or from the D/A Waveform Playback IP Module in loopback mode. Each IP module has an associated memory bank for buffering data in FIFO mode or for storing data in transient capture mode. All memory banks are supported with DMA engines for easily moving A/D data through the PCIe interface. These powerful linked-list DMA engines are capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior to data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely to vary. For each transfer, the DMA engine can automatically construct metadata packets containing A/D channel ID, a sample-accurate time stamp and data length information. These actions simplify the host processor's job of identifying and executing on the data.

In addition to the DDCs, the 53621 features a complete beamforming subsystem. Each DDC core contains programable & Q phase and gain adjustments followed by a power meter that continuously measures the individual average power output. The time constant of the averaging interval for each meter is programmable to 8K samples. The power meters present average power measurements for each DDC core output in easy-to-read registers. In addition, each DDC core includes a threshold detector to automatically send an interrupt to the processor if the average

The Model 53621 factory-installed functions include a sophisticated D/A Waveform Playback IP module. A linkedlist controller allows users to easily play back to the dual D/As waveforms stored in either on-board memory or off-board host memory. Parameters including length of waveform, delay from playback trigger, waveform repetition, etc. can be programmed for each waveform. to 64 individual link entries can be chained together to create complex waveforms with a minimum of programming.

INTERPOLATOR 65536 IP CORE DATA UNPACKING & FLOW CONTROL MUX

Within each A/D Acquisition IP Module is a powerful DDC IP core. Because of the flexible input routing of the A/D Acquisition IP Modules, many different configurations can be achieved including one A/D driving all three DDCs or each of the three A/Ds driving its own DDC. Each DDC has an independent 32-bit tuning frequency

DDC CORE DATA PACKING & FLOW CONTROL MEMORY CONTROL METADATA GENERATOR MUX LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 2 MEMORY CONTROL

DDC CORE DATA PACKING & FLOW CONTROL METADATA GENERATOR MUX LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 3 MEMORY CONTROL

DATA PACKING & FLOW CONTROL METADATA GENERATOR MUX LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 1

The front end accepts three analog or IF inputs on front panel SSMC connectors with transformer coupling into three Texas Instruments ADS5485 200 MHz, 16-bit A/D converters. The digital outputs are delivered into the Virtex-6 FPGA for signal processing, data capture and for routing to other board resources. A front panel 26-pin LVPECL Clock/Sync connector allows multiple boards to be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple boards. Multiple 53621's can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards.

TI DAC5688 DUC (digital upconverter) and D/A accepts a baseband real or complex data stream from the FPGA and provides that input to the upconvert, interpolate and dual D/A stages. When operating as a DUC, it interpolates and translates real or complex baseband input signals to any IF center frequency to 360 MHz. It delivers real or quadrature (I+Q) analog outputs to the dual 16-bit D/A converter. Analog output is through a pair of front panel SSMC connectors. If translation is disabled, the DAC5688 acts as a dual interpolating 16-bit D/A with output sampling rates to 800 MHz. In both modes the DAC5688 provides interpolation factors 2x, 4x and 8x. In addition to the DAC5688, an FPGA-based interpolator core provides additional interpolation from to 65,536x. The two interpolators can be combined to crate a total range from to 524,288x.

The 53621 architecture supports up to four independent memory banks which can be configured with all QDRII+ SRAM, DDR3 SDRAM, or as combination of two banks of each type of memory. Each QDRII+ SRAM bank can 8 MB deep and is an integral part of the module's DMA capabilities, providing FIFO memory space for creating DMA packets. For applications requiring deep memory resources, DDR3 SDRAM banks can each 512 MB deep. Built-in memory functions include an A/D data transient capture mode and D/A waveform playback mode. In addition to the factory-installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes.

The 53621 features a unique high-speed switching configuration. A fabric-transparent crossbar switch bridges numerous interfaces and components on the board using gigabit serial data paths with no latency. Programmable signal input equalization and output pre-emphasis settings enable optimization. Data paths can be selected as single (1X) lanes, or groups of four lanes (4X).

Two internal timing buses provide either a single clock or two different clock rates to the A/D and D/A signal paths. Each timing bus includes a clock, sync and a gate or trigger signal. An on-board clock generator receives an external sample clock from the front panel SSMC connector. This clock can be used directly for either the A/D or D/A sections or can be divided by a built-in clock synthesizer circuit to provide different A/D and D/A clocks. In an alternate mode, the sample clock can be sourced from an on-board programmable VCXO (Voltage-Controlled Crystal Oscillator). In this mode, the front panel SSMC connector can be used to provide a 10 MHz reference clock for synchronizing the internal oscillator.


Technical Parameters

Manufacturer Pentek RoHs Status Lead free / RoHS Compliant
Packing Tape & Reel (TR)/Cut Tape (CT)/Tray/Tube Package/Case

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FAQ:

Q: How does Jotrin guarantee that 53621 is the original manufacturer or agent of Pentek?
We have a professional business development department to strictly test and verify the qualifications of Pentek original manufacturers and agents. All Pentek suppliers must pass the qualification review before they can publish their 53621 devices; we pay more attention to the channels and quality of 53621 products than any other customer. We strictly implement supplier audits, so you can purchase with confidence.
Q: How to find the detailed information of 53621 chips? Including Pentek original factory information, application, 53621 pictures?
You can use Jotrin's intelligent search engine, or filter by Programmable Logic ICs category, or find it through Pentek Information page.
Q: Are the Pentek's 53621 price and stock displayed on the platform accurate?
The Pentek's inventory fluctuates greatly and cannot be updated in time, it will be updated periodically within 24 hours. After submitting an order for 53621, it is recommended to confirm the order with Jotrin salesperson or online customer service before payment.
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Q: What is the process for returns or replacement of 53621?
All goods will implement Pre-Shipment Inspection (PSI), selected at random from all batches of your order to do a systematic inspection before arranging the shipment. If there is something wrong with the 53621 we delivered, we will accept the replacement or return of the 53621 only when all of the below conditions are fulfilled:
(1)Such as a deficiency in quantity, delivery of wrong items, and apparent external defects (breakage and rust, etc.), and we acknowledge such problems.
(2)We are informed of the defect described above within 90 days after the delivery of 53621.
(3)The 53621 is unused and only in the original unpacked packaging.
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(1)Inform us within 90 days
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More details about return electronic components please see our Return & Change Policy.
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