IGL002: The Development Solution of FPGA series

Microsemi's IGL002 FPGA series integrates a fourth-generation flash-based FPGA architecture and high-performance communication interfaces such as PCI EXPRESS (PCIe), XAUI / XGMII, and SERDES and DDR2 / DDR3 memory controllers on a single chip. Mainly used in motor control, system management, industrial automation and high-speed serial I / O applications, such as PCIe, SGMII and user-defined serial ports.

Microsemi's IGL002 FPGA series integrates the fourth-generation flash-based FPGA architecture and high-performance communication interfaces on a single chip. The IGLOO2 series is a low power, reliable and secure programmable logic solution. This new-generation IGLOO2 architecture can provide up to 3.6 times the number of gates, and a 4-input Look-Up-Table architecture. The carry chain provides 2 times the performance and includes multiple embedded memory options and mathblocks For digital signal processing (DSP). High-speed serial interfaces include PCI Express (PCIe), 10Gbps Link Unit Interface (XAUI) / XGMII Extended Sublayer (XGXS), plus native serializer / deserializer (SERDES) communication, and double data Rate 2 (DDR2) / DDR3 memory controller with high-speed memory interface.

Figure 1 IGL002 FPGA block diagramIGL002 high-performance FPGA main features

• IGLOO2 series high-performance FPGA

-Efficient 4-input LUT and carry chain, high performance and low power consumption

-Up to 236 dual-port 18 Kbit SRAMs (large SRAM). Synchronization performance with 400 MHz (512 × 36, 512 × 32, 1kbit × 18 bits, 1kbit × 16, 2kbit × 9, 2kbit × 8, 4kbit × 4, 8kbit × 2, or 16kbit × 1)

-Up to 240 blocks of three-port 1000-bit SRAM, two read ports and one write port (micro SRAM)

-High-performance DSP signal processing, up to 240 fast Mathblocks 18 × 18 signed multiplication, 17 × 17-bit unsigned multiplication, and 44-bit accumulator

• High-speed serial interface

-Up to 16 SERDES channels, each channel supports: XGXS / XAUI expansion (implements 10Gbps (XGMII) Ethernet PHY interface); native SERDES interface for easy implementation of serial RapidIO architecture, or SGMII interface (Soft Ethernet MAC)

-PCI Express (PCIe) endpoint controller X1, X2, X4 lane PCI Express core

-2KB maximum payload

-64-bit / 32-bit AXI / AHB master-slave interface to application layer

• High-speed memory interface

-Up to 2 high-speed DDRX memory controllers

HPMS DDR (MDDR) and Fabric DDR (FDDR) controller

Support LPDDR / DDR2 / DDR3

Clock rate up to 333MHz

SECDED enable / disable function

Supports various DRAM bus width modes, X8, X9, X16, X18, X32, X36

Supports command reordering to optimize memory efficiency

Support data reordering, return key first (per command)

-Support SDRAM through soft SDRAM memory controller

• High-performance memory subsystem

-64 KB of embedded SRAM (eSRAM)

-Up to 512KB of embedded non-volatile memory (eNVM)

-One SPI / COMM_BLK

-DDR bridge (2-port data read / write buffer bridge DDR memory) and 64-bit AXI interface

-Non-blocking, multi-layer AHB bus matrix allows multi-master configuration, supports 5 masters and 7 slaves

-FPGA architecture, two AHB / APB interfaces (master / slave function)

-Two DMA controllers to offload data transactions 8-channel peripheral DMA (PDMA) for data transfer between HPMS peripherals and memory

-High performance DMA (HPDMA) for data transfer between eSRAM and DDR memory

• Clock resources

-Clock source

High-precision 32KHz ~ 20MHz main crystal oscillator

1MHz Embedded RC Oscillator

50MHz built-in RC oscillator

-Up to 8 clock adjustment circuits (CCC) with up to 8 integrated analog PLL output clocks with 8 outputs and 45 ° phase difference (multiplication / division and delay functions)

-Frequency: input 1 ~ 200MHz, output 20 ~ 400 MHz

• Working voltage and I / O

-1.2 V nuclear voltage

-Multi-standard user I / O (MSIO / MSIOD) LVTTL / LVCMOS 3.3V (MSIO only) LVCMOS 1.2V, 1.5V, 1.8V, 2.5V DDR (SSTL2_1, SSTL2_2) LVDS, MLVDS, mini-LVDS, RSDS standard deviation PCI LVPECL (receiver only)

-DDR I / O (DDRIO)

• DDR, DDR2, DDR3, LPDDR, SSTL2, SSTL18, HSTL LVCMOS 1.2 V, 1.5 V, 1.8 V, 2.5 V

-Market-leading number of input / output and 5GSERDES

•safety

-Design security functions (applicable to all devices) Intellectual property (IP) protected encrypted user keys and bitstream loading through unique security functions and new models using the PLD industry,

-Programmable supply chain security device certificates can be enabled in under-trusted areas

-Data security protection function (for advanced equipment)

Uncertainty Random Bit Generator (NRBG)

User encryption services (AES-256, SHA-256, Elliptic Curve Cryptography (ECC) engine)

User Physical Unclonable Function (PUF) Key Registration and Regeneration

CRI Direct DPA Patent Portfolio License

Hardware firewall to protect microcontroller subsystem (HPMS) memory

•reliability

-Single Particle Flip (SEU) immune zero FIT FPGA hive

-Junction temperature: 125 ° C-military temperature, 100 ° C-industrial temperature, 85 ° C-commercial temperature

-Single error correction, double error detection (SECDED)

Protection, as follows:

Embedded Memory (eSRAMs)

PCIe cache

DDR memory controller with optional SECDED mode

-Buffer and SEU anti-latch, as follows: DDR bridge (HPMS, MDDR, FDDR) SPI FIFO

-NVM integrity check (power on and on demand)

-No need for external configuration memory, instant power-on, configuration retained when power is turned off

• Low power consumption

-Low static power and dynamic power Flash * Freeze mode architecture

-Power consumption as low as 13mW / Gbps per channel (SERDES devices)

• Can reduce total power consumption by 25%

IGLOO2 development board M2GL-EVAL-KIT

The IGLOO2 Field Programmable Gate Array (FPGA) Evaluation Kit (M2GL-EVAL-KIT) is RoHS compliant and enables designers to develop one or more of the following applications:

•motor control

•System Management

•automated industry

• High-speed serial I / O applications, such as PCIe,

SGMII, and user-defined serial interface,

Microsemi IGLOO2 Evaluation Kit is a low-cost FPGA platform for developing cost-optimized FPGA designs (using Microsemi's IGLOO2 FPGA), which provides first-class functional integration, and lowest power consumption, highest reliability, and most advanced security Sex. With this IGLOO2 evaluation kit, it is easy to develop transceiver (I / O based) FPGA designs to build PCI Express and Gigabit Ethernet based systems. The motherboard is compatible with the small form factor of PCIe, so any desktop computer or laptop (with a PCIe slot) can be used to quickly build evaluation prototypes.

This kit can: develop and test second-generation PCI Express x1 lane designs; test the signal quality of FPGA transceivers (using full-duplex SERDES SMA pairs); measure the low power consumption of IGLOO2 FPGAs; quickly create operational PCIe links Contains, PCIe control plane demo and several demos coming soon.

The board includes an RJ45 interface to connect 10/100/1000 Ethernet, 512MB of LPDDR, 64MB SPI flash, USB-UART, and I2C, SPI and GPIO headers. The kit includes a 12V power supply, but can also be powered through a PCIe edge connector. It also includes a free gold license for the Libero SoC software toolset to facilitate FPGA development and use the reference designs provided by the kit. Also included is a FlashPro4 JTAG programmer for programming and debugging.