The solution of solar inverter based on Freescale digital signal controllers
These systems range in size from tens of kilowatts of commercial rooftop systems to utility-class centralized power plants that cover up to 100 megawatts and cover several acres.
The inverters of these systems are centralized inverters, but a parallel series of inverters can also be used.
In addition to supplying AC power to the grid, centralized inverters can also be used for power factor correction.
The core advantages of solution
Block diagram of solar inverter based on Freescale digital signal controllers
Introduction of Freescale Digital Signal ControllerMC56F825x/MC56F824x Digital Signal Controller
The MC56F825x/MC56F824x is a member of the 56800E core-based family of digital signal controllers (DSCs).
It combines, on a single chip, the processing power of a DSP and the functionality of a microcontroller with a flexible set of peripherals to create a cost-effective solution. Because of its low cost, configuration flexibility, and compact program code, it is well-suited for many applications.
The MC56F825x/MC56F824x includes many peripherals that are especially useful for cost-sensitive applications, including:
• Industrial control
• Home appliances
• Smart sensors
• Fire and security systems
• Solar inverters
• Battery chargers and management
• Switched-mode power supplies and power management
• Power metering
• Motor control (ACIM, BLDC, PMSM, SR, and stepper)
• Handheld power tools
• Arc detection
• Medical devices/equipment
• Lighting ballast
The 56800E core is based on a modified Harvard-style architecture consisting of three execution units operating in parallel, allowing as many as six operations per instruction
The MCU-style programming model and optimized instruction set allow straightforward generation of efficient,compact DSP and control code. The instruction set is also
highly efficient for C compilers to enable rapid development of optimized control applications.
The MC56F825x/MC56F824x supports program execution from internal memories. Two data operands per instruction cycle can be accessed from the on-chip data RAM. A full set
of programmable peripherals supports various applications.
Each peripheral can be independently shut down to save power. Any pin, except Power pins and the Reset pin, can also be configured as General Purpose Input/Outputs (GPIOs).